High-speed data path testing techniques for non-volatile memory
US10242750B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 31, 2017 |
| Grant date | Mar 26, 2019 |
| Priority date | — |
| Expiry date | May 31, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5602
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques are presented for testing the high-speed data path between the IO pads and the read/write buffer of a memory circuit without the use of an external test device. In an on-chip process, a data test pattern is transferred at a high data rate between the read/write register and a source for the test pattern, such as register for this purpose or the read/write buffer of another plane. The test data after the high-speed transfer is then checked against its expected, uncorrupted value, such as by transferring it back at a lower speed for comparison or by transferring the test data a second time, but at a lower rate, and comparing the high transfer rate copy with the lower transfer rate copy at the receiving end of the transfers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.