Wafer level chip scale package structure and manufacturing method thereof
US10242926B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 29, 2016 |
| Grant date | Mar 26, 2019 |
| Priority date | — |
| Expiry date | Jun 29, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/94
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A wafer level chip scale package (WLCSP) structure and a manufacturing method are disclosed. The WLCSP structure comprises a semiconductor die and a stack. The stack comprises a protective tape and a molding compound. A portion of a first interface surface between the molding compound and the protective tape is curved. The manufacturing method comprises the steps of forming a semiconductor structure; attaching the semiconductor structure on a dummy wafer; performing a first dicing process using a first cutting tool; depositing a molding compound; removing the dummy wafer; performing a second dicing process with a second cutting tool. A first aperture of the first cutting tool is larger than a second aperture of the second cutting tool. The portion of the first interface surface being curved reduces the possibility of generation of cracks in the WLCSP structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.