Nanosheet transistor
US10243061B1 · kind B1 · utility
21Cited by
3References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 15, 2017 |
| Grant date | Mar 26, 2019 |
| Priority date | — |
| Expiry date | Nov 15, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/018
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Inner and outer spacers for nanosheet transistors are formed using techniques that improve junction uniformity. One nanosheet transistor device includes outer spacers and an interlevel dielectric layer liner made from the same material. A second nanosheet transistor device includes outer spacers, inner spacers and an interlevel dielectric layer liner that are all made from the same material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.