Method of uniform channel formation
US10243063B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 8, 2017 |
| Grant date | Mar 26, 2019 |
| Priority date | — |
| Expiry date | Jun 8, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/824
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments described herein generally provide a method and apparatus to form semiconductor devices. Specifically, embodiments describe an apparatus and methods of forming channels in sub-5 nm node FinFETS. The method provides for various processing steps to deposit a dielectric layer over a substrate. The method continues by etching a trench in the dielectric layer, depositing a silicon layer within the trench, depositing a buffer layer on top of the silicon layer in the trench, removing a portion of the buffer layer to form a planar surface, etching the buffer layer into a v-shape, and depositing a channel layer on top of the v-shaped buffer layer. The v-shaped buffer layer advantageously negates facet formation and provides for an InGaAs fin-channel with uniform distribution of indium and gallium throughout the channel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.