FinFET with dielectric isolation after gate module for improved source and drain region epitaxial growth

US10243077B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Eric C. Harley · Lagrangeville, US
• Judson R. Holt · Wappingers Falls, US
• Yue Ke · Fishkill, US
• Rishikesh Krishnan · Poughkeepsie, US
• Keith H. Tabakman · Newburgh, US
• Henry K. Utomo · Ridgefield, US

Key dates

• Filing date: Nov 22, 2017
• Grant date: Mar 26, 2019
• Expiry date: Nov 22, 2037

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/853

Abstract

A method forming a semiconductor device that in one embodiment includes forming a gate structure on a channel region of fin structures, and forming a flowable dielectric material on a source region portion and a drain region portion of the fin structures. The flowable dielectric material is present at least between adjacent fin structures of the plurality of fin structures filling a space between the adjacent fin structures. An upper surface of the source region portion and the drain region portion of fin structures is exposed. An epitaxial semiconductor material is formed on the upper surface of the source region portion and the drain region portion of the fin structures.