Keith H. Tabakman
35Patents
5h-index
67Co-inventors
68Inventor score
Filing activity: Dec 8, 2006 → Jan 15, 2020
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US9812400B1 | Contact line having insulating spacer therein and method of forming same | Electricity | 13 | Active |
| US8492234B2 | Field effect transistor device | Electricity | 10 | Active |
| US8361859B2 | Stressed transistor with improved metastability | Electricity | 9 | Active |
| US10635007B1 | Apparatus and method for aligning integrated circuit layers using multiple grating materials | Electricity | 5 | Active |
| US9613855B1 | Methods of forming MIS contact structures on transistor devices in CMOS applications | Electricity | 5 | Active |
| US10734233B2 | FinFET with high-k spacer and self-aligned contact capping layer | Electricity | 3 | Active |
| US9536900B2 | Forming fins of different semiconductor materials on the same substrate | Electricity | 3 | Active |
| US9312364B2 | finFET with dielectric isolation after gate module for improved source and drain region epitaxial growth | Electricity | 3 | Active |
| US8618617B2 | Field effect transistor device | Electricity | 2 | Active |
| US8815656B2 | Semiconductor device and method with greater epitaxial growth on 110 crystal plane | Electricity | 2 | Active |
| US9059286B2 | Pre-gate, source/drain strain layer formation | Electricity | 2 | Active |
| US9917190B2 | FinFET with dielectric isolation after gate module for improved source and drain region epitaxial growth | Electricity | 1 | Active |
| US10825811B2 | Gate cut first isolation formation with contact forming process mask protection | Electricity | 1 | Active |
| US10580875B2 | Middle of line structures | Electricity | 1 | Active |
| US10991796B2 | Source/drain contact depth control | Electricity | 1 | Active |
| US10262996B2 | Third type of metal gate stack for CMOS devices | Electricity | 1 | Active |
| US10243077B2 | FinFET with dielectric isolation after gate module for improved source and drain region epitaxial growth | Electricity | 1 | Active |
| US9006052B2 | Self aligned device with enhanced stress and methods of manufacture | Electricity | 1 | Active |
| US8426265B2 | Method for growing strain-inducing materials in CMOS circuits in a gate first flow | Electricity | 1 | Active |
| US7895008B2 | Method of performing measurement sampling of lots in a manufacturing process | Emerging Cross-Sectional Technologies | 1 | Active |
| US9831123B2 | Methods of forming MIS contact structures on transistor devices | Electricity | 0 | Active |
| US10192791B1 | Semiconductor devices with robust low-k sidewall spacers and method for producing the same | Electricity | 0 | Active |
| US10615279B2 | FinFET with dielectric isolation after gate module for improved source and drain region epitaxial growth | Electricity | 0 | Active |
| US11081583B2 | FinFET with dielectric isolation after gate module for improved source and drain region epitaxial growth | Electricity | 0 | Active |
| US9634006B2 | Third type of metal gate stack for CMOS devices | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.