Method for fabricating a flash memory
US10243084B2 · kind B2 · utility
0Cited by
8References
9Claims
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Key dates
| Filing date | Sep 28, 2016 |
| Grant date | Mar 26, 2019 |
| Priority date | — |
| Expiry date | Sep 28, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/037
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for fabricating semiconductor device is disclosed. First, a substrate is provided, and a dielectric stack is formed on the substrate, in which the dielectric stack includes a first silicon oxide layer and a first silicon nitride layer. Next, the dielectric stack is patterned, part of the first silicon nitride layer is removed to form two recesses under two ends of the first silicon nitride layer, second silicon oxide layers are formed in the two recesses, a spacer is formed on the second silicon oxide layers, and third silicon oxide layers are formed adjacent to the second silicon oxide layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.