Checking wafer-level integrated designs for antenna rule compliance
US10248755B2 · kind B2 · utility
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19Claims
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Key dates
| Filing date | Mar 2, 2018 |
| Grant date | Apr 2, 2019 |
| Priority date | — |
| Expiry date | Mar 2, 2038 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P90/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and systems for checking a wafer-level design for compliance with a rule include identifying nets that cross chip boundaries for each of a set of chip layouts. Interconnected identified nets are combined into one or more virtual ensembles having properties defined by a sum of properties of the respective interconnected nets. Chip layouts related to virtual ensembles that do not comply with a design rule are modified to bring non-compliant virtual ensembles into compliance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.