Overlay and semiconductor process control using a wafer geometry metric
US10249523B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 21, 2016 |
| Grant date | Apr 2, 2019 |
| Priority date | — |
| Expiry date | Apr 16, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
The present invention may include acquiring a wafer shape value at a plurality of points of a wafer surface at a first and second process level, generating a wafer shape change value at each of the points, generating a set of slope of shape change values at each of the points, calculating a set of process tool correctables utilizing the generated set of slope of shape change values, generating a set of slope shape change residuals (SSCRs) by calculating a slope of shape change residual value at each of the points utilizing the set of process tool correctables, defining a plurality of metric analysis regions distributed across the surface, and then generating one or more residual slope shape change metrics for each metric analysis region based on one or more SSCRs within each metric analysis region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.