Inventor · Santa Clara, CA, US

Sathish Veeraraghavan

15Patents
5h-index
11Co-inventors
59Inventor score

Filing activity: Aug 28, 2009 → Aug 5, 2019

Most-cited inventions

PatentTitleAreaCited byStatus
US8768665B2 Site based quantification of substrate topography and its relation to lithography defocus and overlay Electricity 11 Active
US9354526B2 Overlay and semiconductor process control using a wafer geometry metric Electricity 10 Active
US9430593B2 System and method to emulate finite element model based prediction of in-plane distortions due to semiconductor wafer chucking Electricity 9 Active
US10401279B2 Process-induced distortion prediction and feedforward and feedback correction of overlay errors Electricity 7 Active
US10025894B2 System and method to emulate finite element model based prediction of in-plane distortions due to semiconductor wafer chucking Electricity 6 Active
US8065109B2 Localized substrate geometry characterization Electricity 4 Active
US9865047B1 Systems and methods for effective pattern wafer surface measurement and analysis using interferometry tool Physics 3 Active
US9546862B2 Systems, methods and metrics for wafer high order shape characterization and wafer classification using wafer dimensional geometry tool Physics 3 Active
US10249523B2 Overlay and semiconductor process control using a wafer geometry metric Electricity 2 Active
US9558545B2 Predicting and controlling critical dimension issues and pattern defectivity in wafers using interferometry Physics 1 Active
US9029810B2 Using wafer geometry to improve scanner correction effectiveness for overlay control Electricity 1 Active
US11761880B2 Process-induced distortion prediction and feedforward and feedback correction of overlay errors Electricity 0 Active
US10379061B1 Systems, methods and metrics for wafer high order shape characterization and wafer classification using wafer dimensional geometry tool Physics 0 Active
US9513565B2 Using wafer geometry to improve scanner correction effectiveness for overlay control Electricity 0 Active
US10509329B2 Breakdown analysis of geometry induced overlay and utilization of breakdown analysis for improved overlay control Physics 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.