Inventor · Livermore, CA, US

Jaydeep Sinha

41Patents
7h-index
40Co-inventors
65Inventor score

Filing activity: Dec 22, 2000 → Aug 5, 2019

Most-cited inventions

PatentTitleAreaCited byStatus
US9087176B1 Statistical overlay error prediction for feed forward and feedback correction of overlay errors, root cause analysis and process control Emerging Cross-Sectional Technologies 33 Active
US6538733B2 Ring chuck to hold 200 and 300 mm wafer Electricity 12 Expired
US8768665B2 Site based quantification of substrate topography and its relation to lithography defocus and overlay Electricity 11 Active
US9355440B1 Detection of selected defects in relatively noisy inspection data Physics 11 Active
US9354526B2 Overlay and semiconductor process control using a wafer geometry metric Electricity 10 Active
US9430593B2 System and method to emulate finite element model based prediction of in-plane distortions due to semiconductor wafer chucking Electricity 9 Active
US7324917B2 Method, system, and software for evaluating characteristics of a surface with reference to its edge Electricity 8 Expired
US10401279B2 Process-induced distortion prediction and feedforward and feedback correction of overlay errors Electricity 7 Active
US7853429B2 Curvature-based edge bump quantification Physics 7 Active
US6594002B2 Wafer shape accuracy using symmetric and asymmetric instrument error signatures Electricity 6 Expired
US9779202B2 Process-induced asymmetry detection, quantification, and control using patterned wafer geometry measurements Emerging Cross-Sectional Technologies 6 Active
US10025894B2 System and method to emulate finite element model based prediction of in-plane distortions due to semiconductor wafer chucking Electricity 6 Active
US9177370B2 Systems and methods of advanced site-based nanotopography for wafer surface metrology Physics 5 Active
US7629798B2 Wafer edge-defect detection and capacitive probe therefor Electricity 5 Active
US8065109B2 Localized substrate geometry characterization Electricity 4 Active
US10788759B2 Prediction based chucking and lithography control optimization Physics 4 Active
US9865047B1 Systems and methods for effective pattern wafer surface measurement and analysis using interferometry tool Physics 3 Active
US9707660B2 Predictive wafer modeling based focus error prediction using correlations of wafers Physics 3 Active
US9031810B2 Methods and systems of object based metrology for advanced wafer surface nanotopography Electricity 3 Active
US10352691B1 Systems and methods for wafer structure uniformity monitoring using interferometry wafer geometry tool Physics 3 Active
US9702829B1 Systems and methods for wafer surface feature detection and quantification Physics 3 Active
US9546862B2 Systems, methods and metrics for wafer high order shape characterization and wafer classification using wafer dimensional geometry tool Physics 3 Active
US10249523B2 Overlay and semiconductor process control using a wafer geometry metric Electricity 2 Active
US9632038B2 Hybrid phase unwrapping systems and methods for patterned wafer measurement Physics 2 Active
US8630479B2 Methods and systems for improved localized feature quantification in surface metrology tools Physics 2 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.