Stacked dies using one or more interposers
US10249590B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 6, 2017 |
| Grant date | Apr 2, 2019 |
| Priority date | — |
| Expiry date | Jun 6, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15788
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure generally relates to semiconductor structures and, more particularly, to stacked dies using one or more interposers and methods of manufacture. The structure includes: at least one die comprising a plurality of via interconnects, the plurality of via interconnects comprising at least one functional via interconnect, one defective via interconnect and one redundant functional via interconnect to compensate for the one defective via interconnect; and an interposer which includes interconnects that aligns to and electrically connects the at least one functional via interconnect and the redundant functional via interconnect of different dies when the interposer is oriented in a predetermined orientation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.