Transistor with asymmetric source/drain overlap
US10249755B1 · kind B1 · utility
6Cited by
20References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 22, 2018 |
| Grant date | Apr 2, 2019 |
| Priority date | — |
| Expiry date | Jun 22, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31116
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An asymmetric field-effect transistor having different gate-to-source and gate-to-drain overlaps allows lower parasitic capacitance on the drain side of the device and lower resistance on the source side. Source and drain regions having different configurations can be formed simultaneously using the same precursor materials.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.