Apparatuses for reducing clock path power consumption in low power dynamic random access memory
US10254782B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 30, 2016 |
| Grant date | Apr 9, 2019 |
| Priority date | — |
| Expiry date | Nov 12, 2036 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatus and methods of reducing clock path power consumption are described herein. According to one embodiment, an example apparatus includes a clock control circuit. The clock control circuit includes a command/address domain configured to selectively provide a command/address clock signal based, at least in part, on a chip select signal. The clock control circuit further includes a command domain circuit configured to selectively provide a command clock signal based, at least in part, on the chip select signal. The clock control circuit further includes a column latency domain circuit configured to selectively provide a column latency clock signal based, at least in part, on a memory command. The clock control circuit further includes a four phase domain circuit configured to selectively provide a four phase clock signal based, at least in part on the memory command.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.