Yuan He
133Patents
13h-index
92Co-inventors
89Inventor score
Filing activity: Jan 22, 1999 → Feb 19, 2024
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US9805783B2 | Semiconductor device | Physics | 98 | Active |
| US10170174B1 | Apparatus and methods for refreshing memory | Physics | 91 | Active |
| US10032501B2 | Semiconductor device | Physics | 83 | Active |
| US10339994B2 | Semiconductor device | Physics | 69 | Active |
| US10950289B2 | Semiconductor device | Physics | 61 | Active |
| US10790005B1 | Techniques for reducing row hammer refresh | Physics | 47 | Active |
| US10573370B2 | Apparatus and methods for triggering row hammer address sampling | Physics | 42 | Active |
| US10572377B1 | Row hammer refresh for content addressable memory devices | Emerging Cross-Sectional Technologies | 37 | Active |
| US10468076B1 | Redundancy area refresh rate increase | Physics | 30 | Active |
| US11081160B2 | Apparatus and methods for triggering row hammer address sampling | Physics | 29 | Active |
| US11152050B2 | Apparatuses and methods for multiple row hammer refresh address sequences | Physics | 19 | Active |
| US11302377B2 | Apparatuses and methods for dynamic targeted refresh steals | Physics | 14 | Active |
| US9767919B1 | Systems and methods for testing a semiconductor memory device having a reference memory array | Physics | 14 | Active |
| US10747245B1 | Apparatuses and methods for ZQ calibration | Physics | 10 | Active |
| US10254782B2 | Apparatuses for reducing clock path power consumption in low power dynamic random access memory | Emerging Cross-Sectional Technologies | 9 | Active |
| US10529390B1 | Reduction of ZQ calibration time | Physics | 7 | Active |
| US6383307B1 | Aqueous metal treatment composition | Chemistry; Metallurgy | 7 | Expired |
| US11694738B2 | Apparatuses and methods for multiple row hammer refresh address sequences | Physics | 6 | Active |
| US8486611B2 | Semiconductor constructions and methods of forming patterns | Electricity | 6 | Active |
| US8400634B2 | Semiconductor wafer alignment markers, and associated systems and methods | Electricity | 5 | Active |
| US10917093B1 | Self-adaptive termination impedance circuit | Physics | 5 | Active |
| US10916327B1 | Apparatuses and methods for fuse latch and match circuits | Physics | 4 | Active |
| US11715512B2 | Apparatuses and methods for dynamic targeted refresh steals | Physics | 4 | Active |
| US11087827B1 | Edge memory array mats with sense amplifiers | Electricity | 3 | Active |
| US8815497B2 | Semiconductor constructions and methods of forming patterns | Electricity | 3 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.