Using required arrival time constraints for coupled noise analysis and noise aware timing analysis of out-of-context (OOC) hierarchical entities
US10254784B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 24, 2018 |
| Grant date | Apr 9, 2019 |
| Priority date | — |
| Expiry date | Jul 24, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B3/487
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
Coupled noise from at least one out-of-context aggressor net of an integrated circuit design is computed for an out-of-context victim net. The nets are out-of-context with respect to a hierarchical noise analysis of the integrated circuit design. At least one of the nets is a continuation of a path which extends to at least one in-context portion of the integrated circuit design. An aggressor signal timing window is derived for the at least one out-of-context aggressor net; a victim signal timing window is derived for the out-of-context victim net; and a timing window and noise analysis is completed with the aggressor signal timing window and the victim signal timing window. The aggressor window is derived as a function of required arrival time of the at least one out-of-context aggressor net and/or the victim window is derived as a function of required arrival time of the out-of-context victim net.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.