Steven E. Washburn
8Patents
2h-index
16Co-inventors
48Inventor score
Filing activity: Feb 28, 2000 → Oct 7, 2019
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6571374B1 | Invention to allow multiple layouts for a schematic in hierarchical logical-to-physical checking on chips | Physics | 5 | Expired |
| US6848089B2 | Method and apparatus for detecting devices that can latchup | Physics | 3 | Expired |
| US10254784B1 | Using required arrival time constraints for coupled noise analysis and noise aware timing analysis of out-of-context (OOC) hierarchical entities | Electricity | 1 | Active |
| US10565336B2 | Pessimism reduction in cross-talk noise determination used in integrated circuit design | Physics | 1 | Active |
| US10248753B2 | Pessimism reduction in hierarchical blockage aggressors using estimated resistor and capacitor values | Physics | 1 | Active |
| US10169514B2 | Approximation of resistor-capacitor circuit extraction for thread-safe design changes | Physics | 0 | Active |
| US10552570B2 | Pessimism reduction in hierarchical blockage aggressors using estimated resistor and capacitor values | Physics | 0 | Active |
| US11017137B2 | Efficient projection based adjustment evaluation in static timing analysis of integrated circuits | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.