Debugging system and method
US10255400B1 · kind B1 · utility
6Cited by
9References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 30, 2017 |
| Grant date | Apr 9, 2019 |
| Priority date | — |
| Expiry date | May 27, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2117/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed approaches for configuring a memory include generating by a high-level synthesis (HLS) tool executing on a computer system, a first mapping of elements of a high-level language (HLL) program to elements of a hardware language finite state machine that represents a circuit implementation of the HLL program. The HLS tool further generates a second mapping of lines of the HLL program to states of the hardware language finite state machine and stores the information describing the first mapping and the second mapping in a data structure of a database in the memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.