Warpage control for microelectronics packages
US10256198B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 23, 2017 |
| Grant date | Apr 9, 2019 |
| Priority date | — |
| Expiry date | Mar 24, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/10734
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Techniques for reducing warpage for microelectronic packages are provided. A warpage control layer or stiffener can be attached to a bottom surface of a substrate or layer that is used to attach the microelectronics package to a motherboard. The warpage control layer can have a thickness approximately equal to a thickness of a die of the microelectronics package. A coefficient of thermal expansion of the warpage control layer can be selected to approximately match a CTE of the die. The warpage control layer can be formed from an insulating material or a metallic material. The warpage control layer can comprise multiple materials and can include copper pillar segments to adjust the effective CTE of the warpage control layer. The warpage control layer can be positioned between the microelectronics package and the motherboard, thereby providing warpage control without contributing to the z-height of the microelectronics package.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.