Vertical field-effect-transistors having a silicon oxide layer with controlled thickness

US10256320B1 · kind B1 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Chi-Chun Liu · Altamont, US
• Sanjay C. Mehta · Niskayuna, US
• Luciana Meli · Albany, US
• Muthumanickam Sankarapandian · Niskayuna, US
• Kristin Schmidt · Mountain View, US
• Ankit Vora · San Jose, US

Key dates

• Filing date: Oct 6, 2017
• Grant date: Apr 9, 2019
• Expiry date: Oct 6, 2037

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/83

Abstract

A vertical field-effect transistor and a method for fabricating the same. The vertical field-effect transistor includes a substrate and a bottom source/drain region. The vertical field-effect transistor also includes at least one fin structure, and further includes a bottom spacer layer. The bottom spacer layer has a substantially uniform thickness with a thickness variation of less than 3 nm. A gate structure contacts the bottom spacer layer and at least one fin structure. The method includes forming a structure including a substrate, a source/drain region, and one or more fins. A polymer brush spacer is formed in contact with at least sidewalls of the one or more fins. A polymer brush layer is formed in contact with at least the source/drain region and the polymer brush spacer. The polymer brush spacer is removed. Then, the polymer brush layer is reflowed to the sidewalls of the at least one fin.