Inventor · Niskayuna, NY, US

Sanjay C. Mehta

122Patents
11h-index
118Co-inventors
83Inventor score

Filing activity: Oct 1, 2003 → Apr 7, 2023

Most-cited inventions

PatentTitleAreaCited byStatus
US10418277B2 Air gap spacer formation for nano-scale semiconductor devices Electricity 136 Active
US9773901B1 Bottom spacer formation for vertical transistor Electricity 29 Active
US9892961B1 Air gap spacer formation for nano-scale semiconductor devices Electricity 27 Active
US7517736B2 Structure and method of chemically formed anchored metallic vias Electricity 25 Active
US9397049B1 Gate tie-down enablement with inner spacer Electricity 15 Active
US9356121B2 Divot-free planarization dielectric layer for replacement gate Electricity 13 Active
US8900973B2 Method to enable compressively strained pFET channel in a FinFET structure by implant and thermal diffusion Electricity 12 Active
US7838428B2 Method of repairing process induced dielectric damage by the use of GCIB surface treatment using gas clusters of organic molecular species Electricity 12 Active
US7253105B2 Reliable BEOL integration process with direct CMP of porous SiCOH dielectric Electricity 12 Expired
US9748359B1 Vertical transistor bottom spacer formation Electricity 11 Active
US8617961B1 Post-gate isolation area formation for fin field effect transistor device Electricity 11 Active
US8835237B2 Robust replacement gate integration Electricity 10 Active
US8394684B2 Structure and method for stress latching in non-planar semiconductor devices Electricity 10 Active
US8486778B2 Low resistance source and drain extensions for ETSOI Electricity 9 Active
US10256320B1 Vertical field-effect-transistors having a silicon oxide layer with controlled thickness Electricity 9 Active
US9171927B2 Spacer replacement for replacement metal gate semiconductor devices Electricity 9 Active
US8440552B1 Method to form low series resistance transistor devices on silicon on insulator layer Electricity 8 Active
US8829617B2 Uniform finFET gate height Electricity 8 Active
US9941391B2 Method of forming vertical transistor having dual bottom spacers Electricity 8 Active
US9954103B1 Bottom spacer formation for vertical transistor Electricity 8 Active
US10079299B2 Self aligned top extension formation for vertical transistors Electricity 8 Active
US7294565B2 Method of fabricating a wire bond pad with Ni/Au metallization Electricity 8 Expired
US9748382B1 Self aligned top extension formation for vertical transistors Electricity 8 Active
US9472407B2 Replacement metal gate FinFET Electricity 7 Active
US9583489B1 Solid state diffusion doping for bulk finFET devices Electricity 7 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.