ECC word configuration for system-level ECC compatibility
US10256840B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 20, 2016 |
| Grant date | Apr 9, 2019 |
| Priority date | — |
| Expiry date | Dec 20, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1076
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes memory arrays configured to store pages of data organized into multiple ECC words. The memory device also includes at least one input/output pad for each ECC word associated with a page. The memory device is configurable to perform a first level of error correction on each of the ECC words associated with the page. A system-level error correction circuit is configurable to perform a second level of error correction on the data output by each of the input/output pads during a particular period of time. Each of the one or more input/output pads of the memory device is configurable to provide only one bit of data per ECC word to an external source during an access from an external source.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.