Thomas Andre
46Patents
6h-index
14Co-inventors
58Inventor score
Filing activity: Dec 16, 2011 → Jul 22, 2019
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US9575125B1 | Memory device with reduced test time | Physics | 16 | Active |
| US9311980B1 | Word line supply voltage generator for a memory device and method therefore | Physics | 8 | Active |
| US9183912B2 | Circuit and method for controlling MRAM cell bias voltages | Physics | 8 | Active |
| US9196342B2 | Circuit and method for spin-torque MRAM bit line and source line voltage regulation | Physics | 7 | Active |
| US9286218B2 | Word line auto-booting in a spin-torque magnetic memory having local source lines | Emerging Cross-Sectional Technologies | 7 | Active |
| US8929132B2 | Write driver circuit and method for writing to a spin-torque MRAM | Physics | 7 | Active |
| US9047965B2 | Circuit and method for spin-torque MRAM bit line and source line voltage regulation | Physics | 6 | Active |
| US9529672B2 | ECC word configuration for system-level ECC compatibility | Physics | 5 | Active |
| US9542989B2 | Circuit and method for controlling MRAM cell bias voltages | Physics | 5 | Active |
| US9418001B2 | Memory controller and method for interleaving DRAM and MRAM accesses | Physics | 4 | Active |
| US9502089B2 | Short detection and inversion | Physics | 4 | Active |
| US8976610B2 | Memory device with timing overlap mode | Physics | 4 | Active |
| US10304511B1 | Dual-edge trigger asynchronous clock generation and related methods | Electricity | 3 | Active |
| US9378796B2 | Method for writing to a magnetic tunnel junction device | Physics | 3 | Active |
| US10256840B2 | ECC word configuration for system-level ECC compatibility | Physics | 3 | Active |
| US9007811B1 | Word line driver circuit | Physics | 3 | Active |
| US9218509B2 | Response to tamper detection in a memory device | Physics | 3 | Active |
| US9135970B2 | Tamper detection and response in a memory device | Physics | 3 | Active |
| US11127896B2 | Shared spin-orbit-torque write line in a spin-orbit-torque MRAM | Electricity | 2 | Active |
| US9135965B2 | Memory controller and method for interleaving DRAM and MRAM accesses | Physics | 2 | Active |
| US9230633B2 | Memory device with timing overlap mode | Physics | 2 | Active |
| US10199122B2 | Short detection and inversion | Physics | 2 | Active |
| US9552849B2 | Memory device with timing overlap mode and precharge timing circuit | Physics | 2 | Active |
| US10268591B2 | Delayed write-back in memory | Emerging Cross-Sectional Technologies | 2 | Active |
| US9881695B2 | Short detection and inversion | Physics | 2 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.