Planarization method
US10262869B2 · kind B2 · utility
0Cited by
1References
12Claims
0Family size
Assignees
Inventors
Key dates
| Filing date | Feb 25, 2018 |
| Grant date | Apr 16, 2019 |
| Priority date | — |
| Expiry date | Feb 25, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76819
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A planarization method includes providing a substrate having a semiconductor structure formed thereon. A dielectric layer is formed on the substrate, and a mask layer is formed on the dielectric layer. A first chemical mechanical polishing process is performed to remove a portion of the mask layer thereby forming an opening directly over the semiconductor structure and exposing the dielectric layer. A first etching process is performed to anisotropically remove a portion of the dielectric layer from the opening. The mask layer is then removed and a second chemical mechanical polishing process is then performed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.