Three-dimensional array device having a metal containing barrier and method of making thereof
US10262945B2 · kind B2 · utility
6Cited by
1References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Apr 28, 2017 |
| Grant date | Apr 16, 2019 |
| Priority date | — |
| Expiry date | Jan 30, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D88/00
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A three-dimensional memory device includes driver transistors containing boron doped semiconductor active regions, device contact via structures in physical contact with the boron doped semiconductor active regions, the device contact via structures containing at least one of tantalum, tungsten, and cobalt, and a three-dimensional memory array located over the driver transistors and including an alternating stack of insulating layers and electrically conductive layers and memory structures vertically extending through the alternating stack.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.