Power mesh-on-die trace bumping
US10263106B2 · kind B2 · utility
1Cited by
1References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 31, 2017 |
| Grant date | Apr 16, 2019 |
| Priority date | — |
| Expiry date | Mar 31, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0221
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A power mesh-on-die apparatus includes a solder trace that enhances current flow for a power source trace between adjacent power bumps. The solder trace is also applied between power drain bumps on a power drain trace.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.