Level shifter with improved voltage difference
US10263621B2 · kind B2 · utility
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4References
20Claims
0Family size
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Key dates
| Filing date | Mar 24, 2017 |
| Grant date | Apr 16, 2019 |
| Priority date | — |
| Expiry date | Mar 24, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/018521
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A level shifter that comprises an input operating in an input voltage domain and an output for outputting an output signal in an output voltage domain. The level shifter further includes an inverter circuit operating in the input voltage domain for inverting an input signal to create an inverted input signal. The level shifter also includes an intermediate circuit operating in an intermediate voltage domain for generating an intermediate signal. An output buffer circuit generates the output signal based at least in part on the inverted input signal and the intermediate signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.