Reducing program disturb by modifying word line voltages at interface in two-tier stack after program-verify
US10269435B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 16, 2017 |
| Grant date | Apr 23, 2019 |
| Priority date | — |
| Expiry date | Nov 16, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device and associated techniques for reducing program disturb of memory cells which are formed in a two-tier stack with an increased distance between memory cells at an interface between the tiers. After a verify test in a program loop, a different timing is used for decreasing the word line voltages of the interface memory cells compared to the remaining memory cells. In one aspect, the start of the decrease of the word line voltages of the interface memory cells is delayed. In another aspect, the word line voltages of the interface memory cells is decreased to an intermediate level and held for a time period before being decreased further. In another aspect, the word line voltages of the interface memory cells are decreased at a lower rate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.