Flash memory array with individual memory cell read, program and erase
US10269440B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Dec 9, 2016 |
| Grant date | Apr 23, 2019 |
| Priority date | — |
| Expiry date | Feb 23, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device that provides individual memory cell read, write and erase. In an array of memory cells arranged in rows and columns, each column of memory cells includes a column bit line, a first column control gate line for even row cells and a second column control gate line for odd row cells. Each row of memory cells includes a row source line. In another embodiment, each column of memory cells includes a column bit line and a column source line. Each row of memory cells includes a row control gate line. In yet another embodiment, each column of memory cells includes a column bit line and a column erase gate line. Each row of memory cells includes a row source line, a row control gate line, and a row select gate line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.