Methods of forming semiconductor structures having stair step structures

US10269625B1 · kind B1 · utility

Assignee

• Micron Technology, Inc. · US

Inventors

• John B. Matovu · Boise, US
• David S. Meyaard · Boise, US
• Gowrisankar Damarla · Boise, US
• Sri Sai Sivakumar Vegunta · Boise, US
• Kunal Shrotri · Boise, US
• Shashank Saraf · Boise, US
• Kevin R. Gast · Boise, US
• Jivaan Kishore Jhothiraman · Meridian, US
• Suresh Ramarajan · Boise, US
• Lifang Xu · Boise, US
• Rithu K. Bhonsle · Boise, US
• Rutuparna Narulkar · Boise, US
• Matthew J. King · Boise, US

Key dates

• Filing date: Dec 28, 2017
• Grant date: Apr 23, 2019
• Expiry date: Dec 28, 2037

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B43/50
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method of forming a semiconductor structure includes forming a sacrificial material over a stack comprising alternating levels of a dielectric material and another material, forming an opening through the sacrificial material and at least some of the alternating levels of the dielectric material and the another material, forming at least one oxide material in the opening and overlying surfaces of the sacrificial material, an uppermost surface of the at least one oxide material extending more distal from a surface of a substrate than an uppermost level of the dielectric material and the another material, planarizing at least a portion of the at least one oxide material to expose a portion of the sacrificial material, and removing the sacrificial material while the uppermost surface of the at least one oxide material remains more distal from the surface of the substrate than the uppermost level of the alternating levels of the dielectric material and the another material. Related methods of forming semiconductor structures and related semiconductor devices are disclosed.