Kunal Shrotri
49Patents
7h-index
81Co-inventors
68Inventor score
Filing activity: Apr 19, 2012 → May 17, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US10388665B1 | Methods of forming an array of elevationally-extending strings of memory cells having a stack comprising vertically-alternating insulative tiers and wordline tiers and horizontally-elongated trenches in the stack | Electricity | 38 | Active |
| US10269625B1 | Methods of forming semiconductor structures having stair step structures | Electricity | 24 | Active |
| US9893083B1 | Elevationally-extending strings of memory cells individually comprising a programmable charge storage transistor and methods of processing silicon nitride-comprising materials | Electricity | 17 | Active |
| US10381377B2 | Elevationally-extending strings of memory cells individually comprising a programmable charge storage transistor and methods of processing silicon nitride-comprising materials | Electricity | 14 | Active |
| US10297611B1 | Transistors and arrays of elevationally-extending strings of memory cells | Electricity | 10 | Active |
| US9773805B1 | Integrated structures and methods of forming integrated structures | Electricity | 9 | Active |
| US10014311B2 | Methods of forming an array of elevationally-extending strings of memory cells, methods of forming polysilicon, elevationally-extending strings of memory cells individually comprising a programmable charge storage transistor, and electronic components comprising polysilicon | Electricity | 8 | Active |
| US10600682B2 | Semiconductor devices including a stair step structure, and related methods | Electricity | 4 | Active |
| US10559466B2 | Methods of forming a channel region of a transistor and methods used in forming a memory array | Electricity | 4 | Active |
| US11088017B2 | Stair step structures including insulative materials, and related devices | Electricity | 3 | Active |
| US9153455B2 | Methods of forming semiconductor device structures, memory cells, and arrays | Electricity | 2 | Active |
| US10083984B2 | Integrated structures and methods of forming integrated structures | Electricity | 2 | Active |
| US9064692B2 | DRAM cells and methods of forming silicon dioxide | Electricity | 2 | Active |
| US10096610B1 | Polysilicon doping controlled 3D NAND etching | Electricity | 2 | Active |
| US10157933B2 | Integrated structures including material containing silicon, nitrogen, and at least one of carbon, oxygen, boron and phosphorus | Electricity | 2 | Active |
| US10217755B2 | Flash memory cells, components, and methods | Electricity | 2 | Active |
| US11411013B2 | Microelectronic devices including stair step structures, and related electronic devices and methods | Electricity | 1 | Active |
| US10483407B2 | Methods of forming si3nX, methods of forming insulator material between a control gate and charge-storage material of a programmable charge-storage transistor, and methods of forming an array of elevationally-extending strings of memory cells and a programmable charge-storage transistor manufactured in accordance with methods | Electricity | 1 | Active |
| US10304749B2 | Method and apparatus for improved etch stop layer or hard mask layer of a memory device | Electricity | 1 | Active |
| US11600494B2 | Arrays of elevationally-extending strings of memory cells and methods used in forming an array of elevationally-extending strings of memory cells | Electricity | 0 | Active |
| US11094705B2 | Methods of forming an array of elevationally-extending strings of memory cells, methods of forming polysilicon, elevationally-extending strings of memory cells individually comprising a programmable charge storage transistor, and electronic components comprising polysilicon | Electricity | 0 | Active |
| US11037797B2 | Arrays of elevationally-extending strings of memory cells and methods used in forming an array of elevationally-extending strings of memory cells | Electricity | 0 | Active |
| US11476268B2 | Methods of forming electronic devices using materials removable at different temperatures | Electricity | 0 | Active |
| US10580792B2 | Integrated structures and methods of forming integrated structures | Electricity | 0 | Active |
| US11621270B2 | Methods of forming an array of elevationally-extending strings of memory cells, methods of forming polysilicon, elevationally-extending strings of memory cells individually comprising a programmable charge storage transistor, and electronic components comprising polysilicon | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.