Integrated circuit substrate and method for manufacturing the same
US10269635B2 · kind B2 · utility
0Cited by
3References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 19, 2016 |
| Grant date | Apr 23, 2019 |
| Priority date | — |
| Expiry date | Feb 19, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a wafer. The method includes providing a wafer that includes a plurality of semiconductor device structures, and testing at least one of the plurality of semiconductor device structures. Based on a test result, a liquid is provided on a selected portion of the wafer to selectively alter at least one circuit element within the at least one of the plurality of semiconductor device structures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.