Asymmetric formation of epi semiconductor material in source/drain regions of FinFET devices

US10269932B1 · kind B1 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Ankur Arya · Saratoga Springs, US
• Brian J. Greene · Wappingers Falls, US
• Qun Gao · Clifton Park, US
• Christopher Nassar · Ballston Spa, US
• Junsic Hong · Malta, US
• Vishal Chhabra · Ossining, US

Key dates

• Filing date: Jan 18, 2018
• Grant date: Apr 23, 2019
• Expiry date: Jan 18, 2038

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/038

Abstract

One illustrative method disclosed herein includes, among other things, forming a first fin having first and second opposing sidewalls and forming a first sidewall spacer positioned adjacent the first sidewall and a second sidewall spacer positioned adjacent the second sidewall, wherein the first sidewall spacer has a greater height than the second sidewall spacer. In this example, the method further includes forming epitaxial semiconductor material on the fin and above the first and second sidewall spacers.