Internal clock distortion calibration using DC component offset of clock signal
US10270429B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 20, 2017 |
| Grant date | Apr 23, 2019 |
| Priority date | — |
| Expiry date | Dec 20, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/063
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Several embodiments of electrical circuit devices and systems with clock distortion calibration circuitry are disclosed herein. In one embodiment, an electrical circuit device includes an electrical circuit die having clock distortion calibration circuitry to calibrate a clock signal. The clock distortion calibration circuitry is configured to compare a first duty cycle of a first voltage signal of the clock signal to a second duty cycle of a second voltage signal of the clock signal. Based on the comparison, the clock calibration circuitry is configured to adjust a trim value associated with at least one of the first and the second duty cycles of the first and the second voltage signals, respectively, to calibrate at least one of the first and the second duty cycles and account for duty cycle distortion encountered as the clock signal propagates through a clock tree of the electrical circuit device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.