Inventor · Shanghai, CN

Guan Wang

16Patents

2h-index

18Co-inventors

43Inventor score

Filing activity: Dec 13, 2017 → Jan 17, 2023

Most-cited inventions

Patent	Title	Area	Cited by	Status
US10270429B1	Internal clock distortion calibration using DC component offset of clock signal	Electricity	15	Active
US10727816B2	Internal clock distortion calibration using dc component offset of clock signal	Electricity	2	Active
US11132136B2	Variable width superblock addressing	Physics	1	Active
US10725904B2	Synchronizing NAND logical-to-physical table region tracking	Physics	1	Active
US11594268B2	Memory device deserializer circuit with a reduced form factor	Physics	0	Active
US12073918B2	Memory device deserializer circuit with a reduced form factor	Physics	0	Active
US11733887B2	Write training in memory devices by adjusting delays based on data patterns	Physics	0	Active
US11740819B2	Variable width superblock addressing	Physics	0	Active
US10972078B2	Internal clock distortion calibration using DC component offset of clock signal	Electricity	0	Active
US11079946B2	Write training in memory devices	Physics	0	Active
US11341041B2	Synchronizing NAND logical-to-physical table region tracking	Physics	0	Active
US11336265B2	Internal clock distortion calibration using DC component offset of clock signal	Electricity	0	Active
US11442877B2	Data bus duty cycle distortion compensation	Physics	0	Active
US11201611B2	Duty cycle control circuitry for input/output (I/O) margin control	Electricity	0	Active
US11768782B2	Data bus duty cycle distortion compensation	Physics	0	Active
US12039194B2	Unmap backlog in a memory system	Physics	0	Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.