Combining of several execution units to compute a single wide scalar result
US10275391B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 23, 2017 |
| Grant date | Apr 30, 2019 |
| Priority date | — |
| Expiry date | May 29, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/7867
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit includes reconfigurable units that are reconfigurable to compute a combined result. A first intermediate result of a first reconfigurable unit of the reconfigurable units is exchanged with a second intermediate result of the second reconfigurable unit of the reconfigurable units. The first reconfigurable unit computes a first portion of the combined result utilizing the second intermediate result. The second reconfigurable unit of the reconfigurable units computes a second portion of the combined result utilizing the first intermediate result.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.