Method and apparatus for wafer level packaging
US10276424B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2017 |
| Grant date | Apr 30, 2019 |
| Priority date | — |
| Expiry date | Jun 30, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/96
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus for wafer level packaging are described herein. According to one embodiment, a method comprises depositing an adhesive layer atop a carrier, placing at least a portion of a substrate pre-fabricated with a plurality of die cavities and a plurality of through vias atop the laminate, inserting a die into each of the die cavities, encapsulating the die and the substrate and debonding and removing the laminate and the carrier from the encapsulated die and substrate. Another embodiment provides an apparatus comprising a substrate, a plurality of die cavities formed through the substrate and a plurality of conductive through vias disposed through the substrate and arranged about the perimeter of each die cavity, wherein a top surface of the substrate is exposed for application of an encapsulating layer and a bottom surface of the substrate is exposed for placement on an adhesive layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.