Inventor · Tangxia, CN

Yu Gu

44Patents
9h-index
39Co-inventors
71Inventor score

Filing activity: Jun 20, 2011 → Jun 17, 2022

Most-cited inventions

PatentTitleAreaCited byStatus
US8810024B2 Semiconductor method and device of forming a fan-out PoP device with PWB vertical interconnect units Electricity 44 Active
US10297518B2 Semiconductor device and method of forming supporting layer over semiconductor die in thin fan-out wafer level chip scale package Electricity 43 Active
US10211072B2 Method of reconstituted substrate formation for advanced packaging applications Electricity 32 Active
US10229827B2 Method of redistribution layer formation for advanced packaging applications Electricity 31 Active
US9842798B2 Semiconductor device and method of forming a PoP device with embedded vertical interconnect units Electricity 28 Active
US10049964B2 Semiconductor device and method of forming a fan-out PoP device with PWB vertical interconnect units Electricity 16 Active
US9837303B2 Semiconductor method and device of forming a fan-out device with PWB vertical interconnect units Electricity 12 Active
US9385102B2 Semiconductor device and method of forming supporting layer over semiconductor die in thin fan-out wafer level chip scale package Electricity 11 Active
US9318404B2 Semiconductor device and method of forming stress relieving vias for improved fan-out WLCSP package Electricity 10 Active
US8492203B2 Semiconductor device and method for forming semiconductor package having build-up interconnect structure over semiconductor die with different CTE insulating layers Electricity 8 Active
US9082780B2 Semiconductor device and method of forming a robust fan-out package including vertical interconnects and mechanical support layer Electricity 8 Active
US9865525B2 Semiconductor method and device of forming a fan-out PoP device with PWB vertical interconnect units Electricity 7 Active
US8456002B2 Semiconductor device and method of forming insulating layer disposed over the semiconductor die for stress relief Electricity 6 Active
US9875973B2 Semiconductor device and method for forming semiconductor package having build-up interconnect structure over semiconductor die with different CTE insulating layers Electricity 5 Active
US10446479B2 Semiconductor device and method of forming a PoP device with embedded vertical interconnect units Electricity 3 Active
US11024561B2 Semiconductor device and method of forming a fan-out PoP device with PWB vertical interconnect units Electricity 2 Active
US10707150B2 Semiconductor device and method of forming a fan-out PoP device with PWB vertical interconnect units Electricity 2 Active
US9252092B2 Semiconductor device and method of forming through mold hole with alignment and dimension control Electricity 2 Active
US8759155B2 Semiconductor device and method of forming insulating layer disposed over the semiconductor die for stress relief Electricity 2 Active
US10818841B2 Method of fabricating organic light emitting diode display Electricity 1 Active
US9666500B2 Semiconductor device and method of forming insulating layer disposed over the semiconductor die for stress relief Electricity 1 Active
US11283029B2 Thermally activated delayed fluorescence material, organic electroluminescent device, and display panel Electricity 1 Active
US10170385B2 Semiconductor device and method of forming stacked vias within interconnect structure for FO-WLCSP Electricity 1 Active
US11205756B2 Green light thermally activated delayed fluorescence (TADF) material and application thereof Electricity 1 Active
US10276424B2 Method and apparatus for wafer level packaging Electricity 1 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.