Thermal atomic layer etching processes
US10280519B2 · kind B2 · utility
14Cited by
4References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 7, 2017 |
| Grant date | May 7, 2019 |
| Priority date | — |
| Expiry date | Dec 7, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31138
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Thermal atomic layer etching processes are disclosed. In some embodiments, the methods comprise at least one etch cycle in which the substrate is alternately and sequentially exposed to a first vapor phase halide reactant and a second vapor halide reactant. In some embodiments, the first reactant may comprise an organic halide compound. During the thermal ALE cycle, the substrate is not contacted with a plasma reactant.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.