Techniques and circuits for on-chip jitter and phase noise measurement in a digital test environment
US10281523B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 19, 2017 |
| Grant date | May 7, 2019 |
| Priority date | — |
| Expiry date | Nov 23, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/85
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Proposed digital on-chip jitter and phase noise measurement techniques and circuits are presented and include the use of a digitally controlled delay locked loop having very fine resolution but limited range to track the phase error between the tested device output clock and its reference clock. Some implementations employ a combination of a high-gain 1-bit phase detector, a digital accumulator and a fine digitally controlled delay element to track the accumulated phase difference between the reference clock and the device under test. Observing the accumulator output is an indication of the jitter and performing a Fast Fourier Transform of the accumulator output provides the phase noise of the device under test.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.