Memory devices with programmable latencies and methods for operating the same
US10282133B2 · kind B2 · utility
2Cited by
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19Claims
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Key dates
| Filing date | Aug 31, 2017 |
| Grant date | May 7, 2019 |
| Priority date | — |
| Expiry date | Aug 31, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/229
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device is provided. The memory device includes a memory array, operation circuitry configured to perform a memory operation in the memory array in response to a command received from a connected host device, and delay circuitry configured to delay the performance of the memory operation in response to one or more bits received with the command. The one or more bits indicate a duration by which to delay the performance of the memory operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.