Methods of synchronizing memory operations and memory systems employing the same
US10282134B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 31, 2017 |
| Grant date | May 7, 2019 |
| Priority date | — |
| Expiry date | Aug 31, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/222
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system is provided. The memory system includes a first memory device having a first latency corresponding to a first command and a second memory device having a second latency corresponding to a second command. The second latency differs from the first latency by a latency difference. The memory system further includes a host operably coupled to the first and second memory devices. The host is configured to send the first command to the first memory device at a first time, and to send the second command to the second memory device at a second time. The first time and the second time are separated by a delay corresponding to the latency difference.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.