Reducing cache footprint in cache coherence directory
US10282295B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 29, 2017 |
| Grant date | May 7, 2019 |
| Priority date | — |
| Expiry date | Nov 29, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/621
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method includes monitoring, at a cache coherence directory, states of cachelines stored in a cache hierarchy of a data processing system using a plurality of entries of the cache coherence directory. Each entry of the cache coherence directory is associated with a corresponding cache page of a plurality of cache pages, and each cache page representing a corresponding set of contiguous cachelines. The method further includes selectively evicting cachelines from a first cache of the cache hierarchy based on cacheline utilization densities of cache pages represented by the corresponding entries of the plurality of entries of the cache coherence directory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.