Inventor · Bellevue, WA, US

Yasuko Eckert

77Patents
5h-index
79Co-inventors
71Inventor score

Filing activity: Dec 9, 2012 → Apr 3, 2024

Most-cited inventions

PatentTitleAreaCited byStatus
US9443561B1 Ring networks for intra- and inter-memory I/O including 3D-stacked memories Emerging Cross-Sectional Technologies 19 Active
US9286948B2 Query operations for stacked-die memory device Electricity 7 Active
US10452437B2 Temperature-aware task scheduling and proactive power management Emerging Cross-Sectional Technologies 5 Active
US11625251B1 Mechanism for reducing coherence directory controller overhead for near-memory compute elements Physics 5 Active
US9372803B2 Method and system for shutting down active core based caches Emerging Cross-Sectional Technologies 5 Active
US9524164B2 Specialized memory disambiguation mechanisms for different memory read access types Physics 5 Active
US9251081B2 Management of caches Emerging Cross-Sectional Technologies 5 Active
US10282295B1 Reducing cache footprint in cache coherence directory Physics 4 Active
US9110671B2 Idle phase exit prediction Emerging Cross-Sectional Technologies 4 Active
US9251069B2 Mechanisms to bound the presence of cache blocks with specific properties in caches Emerging Cross-Sectional Technologies 3 Active
US10705958B2 Coherency directory entry allocation based on eviction costs Physics 3 Active
US9947386B2 Thermal aware data placement and compute dispatch in a memory system Physics 3 Active
US10719441B1 Using predictions of outcomes of cache memory access requests for controlling whether a request generator sends memory access requests to a memory in parallel with cache memory access requests Physics 3 Active
US10097091B1 Setting operating points for circuits in an integrated circuit chip Electricity 2 Active
US9298615B2 Methods and apparatus for soft-partitioning of a data cache for stack data Emerging Cross-Sectional Technologies 2 Active
US9378153B2 Early write-back of modified data in a cache memory Emerging Cross-Sectional Technologies 2 Active
US11921634B2 Leveraging processing-in-memory (PIM) resources to expedite non-PIM instructions executed on a host Physics 2 Active
US10133678B2 Method and apparatus for memory management Emerging Cross-Sectional Technologies 2 Active
US11922107B2 Quantum circuit mapping for multi-programmed quantum computers Physics 2 Active
US10303602B2 Preemptive cache management policies for processing units Physics 2 Active
US10838864B2 Prioritizing local and remote memory access in a non-uniform memory access architecture Physics 1 Active
US10339067B2 Mechanism for reducing page migration overhead in memory systems Physics 1 Active
US9658663B2 Thermally-aware throttling in a three-dimensional processor stack Emerging Cross-Sectional Technologies 1 Active
US9507410B2 Decoupled selective implementation of entry and exit prediction for power gating processor components Emerging Cross-Sectional Technologies 1 Active
US10970120B2 Method and system for opportunistic load balancing in neural networks using metadata Physics 1 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.