Reducing disturbs with delayed ramp up of selected word line voltage after pre-charge during programming
US10283202B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 16, 2017 |
| Grant date | May 7, 2019 |
| Priority date | — |
| Expiry date | Nov 16, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/32
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device and associated techniques for reducing hot electron injection type of disturbs of memory cells. In one approach, after a pre-charge operation, voltages of a first group of adjacent word lines comprising a selected word line (WLn) and one or more drain-side word lines of WLn are increased after voltages of remaining word lines are increased. In another approach, after the pre-charge operation, voltages of the first group of adjacent word lines are increased in steps while voltages of remaining word lines are continuously increased. In another approach, voltages of the first group of adjacent word lines are increased from a negative voltage while voltages of remaining word lines are increased from 0 V. In another aspect, the disturb countermeasures can be implemented according to the position of WLn in a multi-tier stack.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.