Method of depositing charge trapping polycrystalline silicon films on silicon substrates with controllable film stress
US10283402B2 · kind B2 · utility
2Cited by
22References
60Claims
0Family size
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Key dates
| Filing date | Feb 25, 2016 |
| Grant date | May 7, 2019 |
| Priority date | — |
| Expiry date | Feb 25, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/201
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor on insulator multilayer structure is provided. The multilayer comprises a high resistivity single crystal semiconductor handle substrate, a textured oxide, nitride, or oxynitride layer, a polycrystalline silicon layer, a dielectric layer, and a single crystal semiconductor device layer. The multilayer structure is prepared in a manner that reduces wafer bow.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.