Method of fabricating 3-dimensional fan-out structure
US10283477B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 18, 2016 |
| Grant date | May 7, 2019 |
| Priority date | — |
| Expiry date | Dec 11, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating a 3D fan-out structure for an integrated circuit device includes providing a substrate carrier having first and second opposing surfaces and an aperture extending between the first and second surfaces. A first semiconductor die is bonded to the first surface of the substrate carrier such that the first die covers the aperture of the substrate carrier. An encapsulant and a second die are deposited within the aperture of the substrate carrier such that an active surface of the second die is exposed and coplanar with the second surface of the substrate carrier. One or more redistribution layers are then applied on the second surface of the substrate carrier to form a 3D fan-out structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.