Ultrahigh selective polysilicon etch with high throughput
US10283615B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 11, 2015 |
| Grant date | May 7, 2019 |
| Priority date | — |
| Expiry date | Jun 28, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/024
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Provided are methods and apparatuses for removing a polysilicon layer on a wafer, where the wafer can include a nitride layer, a low-k dielectric layer, an oxide layer, and other films. A plasma of a hydrogen-based species and a fluorine-based species is generated in a remote plasma source, and the wafer is exposed to the plasma at a relatively low temperature to limit the formation of solid byproduct. In some implementations, the wafer is maintained at a temperature below about 60° C. The polysilicon layer is removed at a very high etch rate, and the selectivity of polysilicon over the nitride layer and the oxide layer is very high. In some implementations, the wafer is supported on a wafer support having a plurality of thermal zones configured to define a plurality of different temperatures across the wafer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.