Semiconductor structure and method for forming the same
US10283624B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 19, 2018 |
| Grant date | May 7, 2019 |
| Priority date | — |
| Expiry date | Jan 19, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/671
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device and a method for forming the same are provided. The method includes forming a gate structure over a fin structure. The method further includes forming first gate spacers on opposite sidewalls of the gate structure. The method further includes forming source/drain features in the fin structure and adjacent to the first gate spacers. The method further includes performing a surface treatment process on top surfaces of the source/drain features and outer sidewalls of the first gate spacers. The method further includes depositing a contact etch stop layer (CESL) over the source/drain features and the first gate spacers. A first portion of the CESL is deposited over the top surfaces of the source/drain features at a first deposition rate. A second portion of the CESL is deposited over the outer sidewalls of the first gate spacers at a second deposition rate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.