Patent · US Active

Systems and methods for reuse of delay calculation in static timing analysis

US10289774B1 · kind B1 · utility

5Cited by

7References

20Claims

0Family size

Assignee

Cadence Design Systems, Inc. · US

Inventors

Pradeep Yadav · Greater Noida, IN
Ratnakar Goyal · New Delhi, IN
Prashant Sethia · Noida, IN
Manuj Verma · Noida, IN

Key dates

Filing date	Mar 30, 2017
Grant date	May 14, 2019
Priority date	—
Expiry date	May 27, 2037

Classification

Technology area (CPC G)Physics
CPC primaryG06F2119/12
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Various embodiments describe performing static timing analysis (STA) on a circuit design such that delay timing calculation results generated by an STA on the circuit design can be reused by subsequent STAs on the circuit design in place of performing a set of delay timing calculations on the circuit design.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.